The present invention relates to a digital broadcast receiver for receiving a digital broadcast signal in which a compressed video signal, a compressed audio signal, and a data signal in association with the compressed video and audio signals are multiplexed, as well as a CPU and a decoder used for the digital broadcast.
FIG. 9 shows a typical configuration of a conventional digital broadcast receiver for receiving digitally compressed digital broadcast that is defined by the ISO/IEC 13818 standard and usually abbreviated as MPEG2.
The digital broadcast receiver shown in the figure comprises a tuner/FEC (Forward Error Correctioner) 10, an antenna 11, a demultiplexer 20, a CPU 30, a memory 40, a decoder buffer 50, a video decoder 60, data selectors 70 and 90, an audio decoder 80, a CPU interface 100, a display 110, a speaker 120, and a data bus 130.
The electric waves of digital broadcast received by the antenna 11 are amplified and detected by a tuner in the tuner/FEC 10, and then subjected to FEC (Forward Error Correction), so that the electric waves of the digital broadcast are converted into a digital signal. The digital signal is sent to the demultiplexer 20. The demultiplexer 20 separates a digital broadcast signal obtained from the tuner/FEC 10, in which signal a compressed video signal, a compressed audio signal, and a data signal are multiplexed, to supply the compressed video signal and the compressed audio signal to the decoder buffer 50 and supply the data signal to the memory 40 via the data bus 130.
The decoder buffer 50 retains the compressed video signal and the compressed audio signal. The video decoder 60 reads the compressed video signal from the decoder buffer 50, decodes the signal according to a PTS (Presentation Time Stamp), and sends the result of signal decoding to the selector 70. The audio decoder 80 reads the compressed audio signal from the decoder buffer 50, decodes the signal according to a PTS, and sends the result of signal decoding to the selector 90. The memory 40 accumulates the data signal mentioned above, and also stores programs to be executed by the CPU 30, which will be described below. The CPU 30 executes, by time division, a plurality of programs such as a data decoder 42, an OSD (On Screen Display) 43, a system control 44, and the like extracted to an execution program area 41 of the memory 40, and accordingly supplies a data signal to the data bus 130, which will be described later. The data decoder 42 analyzes the header portion of the data signal, and decodes the data signal according to the type of data indicated in the header portion of the data signal. The OSD 43 performs calculations for image rendering necessary for OSD display. The system control 44 controls the entire digital broadcast receiver.
The CPU interface 100 obtains from the data bus 130 a video signal and an audio signal decoded by the data decoder 42, a program executed by the CPU 30. The CPU interface 100 then supplies the video signal and the audio signal to the selector 70 or the selector 90 according to the signal type obtained, and sends a control signal to the selector 70 or the selector 90. According to the control signal from the CPU 30, the selector 70 selects the output of the video decoder 60 when broadcast, the main signal, is to be outputted, and selects the video signal supplied from the CPU interface 100 and supplies the video signal to the display 110, which will be described below, when the video signal included in the data signal is to be outputted. According to the control signal from the CPU 30, the selector 90 selects the output of the audio decoder 80 when broadcast, the main signal, is to be outputted, and selects the audio signal supplied from the CPU interface 100 and supplies the audio signal to the speaker 120, which will be described below, when the audio signal included in the data signal is to be outputted. The display 110 displays the video signal supplied from the selector 70. The speaker 120 outputs the audio signal supplied from the selector 90. The data bus 130 is a path for transmitting the data signal processed by the CPU 30 to each part in the digital broadcast receiver.
According to the configuration described above, if a data signal is multiplexed in a digital broadcast signal, a display and an audio output can be obtained by subjecting the data signal to software decoding by the data decoder 42.
Incidentally, there is disclosed in Japanese Patent Laid-open No. Hei 07-264562 an example of a digital broadcast receiver that decodes a digital broadcast signal in which a compressed video signal, a compressed audio signal, and an accompanying data signal are multiplexed.